| CAMeleon: Reconfigurable B(T)CAM in Computational RAM | 0 | 0.34 | 2021 |
| DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators | 1 | 0.36 | 2021 |
| PIMBALL: Binary Neural Networks in Spintronic Memory | 4 | 0.51 | 2020 |
| MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications | 0 | 0.34 | 2020 |
| SeFAct - selective feature activation and early classification for CNNs. | 1 | 0.36 | 2019 |
| NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients | 0 | 0.34 | 2019 |
| True In-memory Computing with the CRAM: From Technology to Applications | 0 | 0.34 | 2019 |
| DAG based library-free technology mapping | 8 | 0.60 | 2007 |
| Technology mapping algorithm targeting routing congestion under delay constraints | 1 | 0.36 | 2006 |
| Placement of thermal vias in 3-D ICs using various thermal objectives | 53 | 2.70 | 2006 |
| Accurate estimation of global buffer delay within a floorplan | 25 | 1.40 | 2006 |
| Logical effort based technology mapping | 4 | 0.44 | 2004 |
| Analysis and optimization of structured power/ground networks | 10 | 0.77 | 2003 |
| A timing-constrained simultaneous global routing algorithm | 19 | 1.10 | 2002 |
| Hierarchical analysis of power distribution networks | 131 | 7.21 | 2002 |
| Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model | 5 | 0.47 | 2000 |
| A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates] | 40 | 2.74 | 2000 |
| Non-Hanan routing | 17 | 1.01 | 1999 |
| Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits | 45 | 2.31 | 1996 |
| Wire sizing as a convex optimization problem: exploring the area-delay tradeoff | 18 | 1.55 | 1996 |
| Convexity-based algorithms for design centering | 14 | 1.91 | 1994 |
