Daisuke Suzuki - Citegraph

Author Info

Name	Affiliation	Papers
DAISUKE SUZUKI	Mitsubishi Electr Corp, Informat Technol R&D Ctr, Kamaishi, Iwate 2478501, Japan	27
Collaborators	Citations	PageRank
31	306	21.80
Referers	Referees	References
542	301	196

Search Limit

100542

Publications (27 rows)

Collaborators (31 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Towards Trained Model Confidentiality And Integrity Using Trusted Execution Environments	0	0.34	2021
Adversarial Black-Box Attacks With Timing Side-Channel Leakage	0	0.34	2021
An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis	0	0.34	2020
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar	2	0.37	2019
SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation.	0	0.34	2018
Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack.	0	0.34	2018
Asymmetric Leakage From Multiplier And Collision-Based Single-Shot Side-Channel Attack	0	0.34	2016
Two Operands Of Multipliers In Side-Channel Attack	4	0.42	2015
PUF as a sensor	0	0.34	2015
Reversing stealthy dopant-level circuits	7	0.52	2015
Unified Coprocessor Architecture For Secure Key Storage And Challenge-Response Authentication	1	0.37	2014
Glitch Puf: Extracting Information From Usually Unwanted Glitches	9	0.54	2012
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI	4	0.45	2012
How To Decide Selection Functions For Power Analysis: From The Viewpoint Of Hardware Architecture Of Block Ciphers	0	0.34	2011
How To Maximize The Potential Of Fpga-Based Dsps For Modular Exponentiation	8	0.49	2011
High-Speed Passphrase Search System For Pgp	0	0.34	2010
The glitch PUF: a new delay-PUF architecture exploiting glitch shapes	30	1.38	2010
A Design Methodology For A Dpa-Resistant Circuit With Rsl Techniques	2	0.37	2010
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques	22	0.94	2009
Security Evaluations of MRSL and DRSL Considering Signal Delays	2	0.39	2008
High-Speed Search System for PGP Passphrases	2	0.43	2008
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style	5	0.46	2008
Leakage Analysis of DPA Countermeasures at the Logic Level	3	0.43	2007
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level	39	2.39	2007
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style	83	2.94	2006
DPA leakage models for CMOS logic circuits	29	1.88	2005
Random Switching Logic: A Countermeasure against DPA based on Transition Probability	54	3.98	2004