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| Unifying Timer And Interrupt Management For An Arm-Risc-V-Heterogeneous Multi-Core | 0 | 0.34 | 2020 |
| Context Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs | 0 | 0.34 | 2019 |
| A Parameterizable Feedback FxLMS Architecture for FPGA Platforms | 0 | 0.34 | 2019 |
| Low-Latency Fir Filter Structures Targeting Fpga Platforms | 0 | 0.34 | 2018 |
| Operating System Concepts for Reconfigurable Computing: Review and Survey. | 0 | 0.34 | 2016 |
| A Threat-Model For Building And Home Automation | 1 | 0.38 | 2016 |
| Wireless Sensor/Actuator Device Configuration By Nfc | 2 | 0.43 | 2016 |
| Clock speed optimization of runtime reconfigurable systems by signal latency measurement | 0 | 0.34 | 2015 |
| Multicore reconfiguration platform an alternative to RAMPSoC | 1 | 0.38 | 2011 |
| A Computer Architecture with Hardwarebased Malware Detection | 0 | 0.34 | 2010 |
| Konrad-Zuse-Workshop. Rechnender Raum und Zellulare Automaten (Vorwort) | 0 | 0.34 | 2010 |
| List of Criteria for a Secure Computer Architecture | 4 | 0.56 | 2009 |
| Unsupervised Segmentation of Naval Infrared Images through a Markov Random Field Model | 0 | 0.34 | 2006 |
| Extraction Of Ship Silhouettes Using Active Contours From Infrared Images | 2 | 0.43 | 2005 |
| The SDVM: A Self Distributing Virtual Machine for Computer Clusters | 2 | 0.45 | 2004 |
| The CDAG: a data structure for automatic parallelization for a multithreaded architecture | 5 | 0.62 | 2002 |
| SDAARC: An Extended Cache-Only Memory Architecture | 5 | 0.63 | 2002 |
| The SDAARC Architecture | 4 | 0.56 | 2001 |
| Hybrides Scheduling | 0 | 0.34 | 1999 |
| Prozessorarchitekturen für J2K | 0 | 0.34 | 1999 |
| Combining static partitioning with dynamic distribution of threads | 4 | 0.53 | 1998 |
| Automatic scheduling for cache only memory architectures | 5 | 0.57 | 1998 |
| Compiler Technology for Two Novel Computer Architectures | 1 | 0.38 | 1997 |
| What Computer Architecture Can Learn From Computational Intelligence - And Vice Versa | 0 | 0.34 | 1997 |
| A Combined Virtual Shared Memory and Network which Schedules | 5 | 0.57 | 1997 |
| Neural Compiler Technology for a Parallel Architecture | 2 | 0.43 | 1996 |
| ADARC: A New Multi-Instruction Issue Approach | 4 | 0.73 | 1996 |
| Mapping of Neural Networks onto Data Flow Graphs | 1 | 0.35 | 1996 |
| The AM3 associative processor | 0 | 0.34 | 1995 |
| The MHD Memory | 1 | 0.43 | 1993 |
| An Object-Oriented Pen-Based Recognizer for Handprinted Characters | 1 | 0.52 | 1993 |
| Möglichkeiten zur Parallelisierung des Error-Backpropagation Algorithmus | 0 | 0.34 | 1991 |
