| Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog | 1 | 0.35 | 2022 |
| Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs) | 0 | 0.34 | 2021 |
| Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs | 0 | 0.34 | 2021 |
| Stochastic Dividers for Low Latency Neural Networks | 1 | 0.36 | 2021 |
| Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning | 2 | 0.37 | 2021 |
| Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation | 1 | 0.35 | 2021 |
| Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design | 0 | 0.34 | 2021 |
| Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders | 0 | 0.34 | 2021 |
| A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses | 1 | 0.35 | 2021 |
| Improving Packet Flow Counting With Fingerprint Counting | 0 | 0.34 | 2020 |
| Cuckoo Filters and Bloom Filters: Comparison and Application to Packet Classification | 3 | 0.41 | 2020 |
| FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs | 0 | 0.34 | 2020 |
| Fast Updates for Line-Rate HyperLogLog-Based Cardinality Estimation | 0 | 0.34 | 2020 |
| Codes for Limited Magnitude Error Correction in Multilevel Cell Memories | 0 | 0.34 | 2020 |
| Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs | 0 | 0.34 | 2020 |
| Scheme for periodical concurrent fault detection in parallel CRC circuits | 1 | 0.38 | 2020 |
| Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs | 0 | 0.34 | 2020 |
| Tradeoffs in optical packet and circuit transport of fronthaul traffic: the time for SBVT? | 0 | 0.34 | 2020 |
| When filtering is not possible caching negatives with fingerprints comes to the rescue | 0 | 0.34 | 2020 |
| Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine | 0 | 0.34 | 2020 |
| Error-Tolerant Computation For Voting Classifiers With Multiple Classes | 0 | 0.34 | 2020 |
| Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes | 0 | 0.34 | 2020 |
| Protection Scheme for Star Tracker Images | 0 | 0.34 | 2019 |
| The Tandem Counting Bloom Filter - It Takes Two Counters to Tango | 2 | 0.40 | 2019 |
| Low Delay 3-Bit Burst Error Correction Codes | 0 | 0.34 | 2019 |
| Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction | 0 | 0.34 | 2019 |
| Spectrum/Space Switching and Multi-Terabit Transmission in Agile Optical Metro Networks | 0 | 0.34 | 2019 |
| Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells | 0 | 0.34 | 2019 |
| Efficient Concurrent Error Detection for SEC-DAEC Encoders | 0 | 0.34 | 2019 |
| Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC). | 2 | 0.40 | 2019 |
| Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes. | 0 | 0.34 | 2019 |
| Enhancing Instruction TLB Resilience to Soft Errors. | 0 | 0.34 | 2019 |
| Error Detection and Correction in SRAM Emulated TCAMs. | 0 | 0.34 | 2019 |
| Optical Interconnection of CDN Caches with Tb/s Sliceable Bandwidth-Variable Transceivers featuring Dynamic Restoration | 1 | 0.48 | 2019 |
| Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation | 0 | 0.34 | 2019 |
| A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. | 0 | 0.34 | 2018 |
| A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs. | 0 | 0.34 | 2018 |
| An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications. | 1 | 0.37 | 2018 |
| Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays | 0 | 0.34 | 2018 |
| Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. | 1 | 0.37 | 2018 |
| Efficient Fault-Tolerant Design for Parallel Matched Filters. | 2 | 0.40 | 2018 |
| Efficient Implementations of 4-Bit Burst Error Correction for Memories. | 1 | 0.36 | 2018 |
| Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders | 0 | 0.34 | 2018 |
| Position-aware cuckoo filters. | 1 | 0.37 | 2018 |
| Elastic Networks Thematic Network Results Ii: Edge Computing And Wireless Support | 0 | 0.34 | 2018 |
| Adaptive Cuckoo Filters | 3 | 0.39 | 2018 |
| Seu and Sefi error detection and correction on a ddr3 memory system | 0 | 0.34 | 2018 |
| CuCoTrack: Cuckoo Filter Based Connection Tracking. | 0 | 0.34 | 2018 |
| Combined Modular Key and Data Error Protection for Content-Addressable Memories. | 0 | 0.34 | 2017 |
| Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. | 5 | 0.63 | 2017 |
