| Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices | 0 | 0.34 | 2020 |
| Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols | 0 | 0.34 | 2018 |
| MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. | 1 | 0.36 | 2018 |
| Task Scheduling Based Redundant Task Allocation Method For The Multi-Core Systems With The Dttr Scheme | 0 | 0.34 | 2017 |
| Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance | 0 | 0.34 | 2016 |
| A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks | 0 | 0.34 | 2016 |
| An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis | 2 | 0.39 | 2016 |
| The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs | 2 | 0.38 | 2016 |
| A task allocation method for the DTTR scheme based on task scheduling of fault patterns | 1 | 0.39 | 2016 |
| Dependable real-time task execution scheme for a many-core platform | 2 | 0.45 | 2015 |
| Novel Implementation Method Of Multiple-Way Asynchronous Arbiters | 0 | 0.34 | 2015 |
| A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits | 0 | 0.34 | 2015 |
| Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. | 0 | 0.34 | 2014 |
| High-Throughput Partially Parallel Inter-Chip Link Architecture For Asynchronous Multi-Chip Nocs | 0 | 0.34 | 2014 |
| An NoC-based evaluation platform for safety-critical automotive applications | 2 | 0.40 | 2014 |
| Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits | 0 | 0.34 | 2014 |
| Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits | 2 | 0.39 | 2014 |
| Fault Diagnosis And Reconfiguration Method For Network-On-Chip Based Multiple Processor Systems With Restricted Private Memories | 3 | 0.42 | 2013 |
| Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). | 0 | 0.34 | 2013 |
| Dependable routing in multi-chip NoC platforms for automotive applications | 4 | 0.62 | 2012 |
| An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip | 3 | 0.56 | 2012 |
| Performance Modeling and Analysis of On-chip Networks for Real-Time Applications | 1 | 0.35 | 2012 |
| Multi-chip NoCs for Automotive Applications | 7 | 0.61 | 2012 |
| Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories | 0 | 0.34 | 2011 |
| Improving Dependability and Performance of Fully Asynchronous On-chip Networks | 20 | 1.11 | 2011 |
| A Dynamic Link-Width Optimization for Network-on-Chip | 0 | 0.34 | 2011 |
| Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement | 6 | 0.42 | 2010 |
| A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs | 6 | 0.58 | 2010 |
| N-way ring and square arbiters | 1 | 0.38 | 2009 |
| A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. | 1 | 0.36 | 2009 |
| Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs | 1 | 0.36 | 2009 |
| A Conservative Framework for Safety-Failure Checking | 0 | 0.34 | 2008 |
| Asynchronous pipeline controller based on early acknowledgement protocol | 4 | 0.48 | 2008 |
| Hazard Checking of Timed Asynchronous Circuits Revisited | 1 | 0.35 | 2008 |
| Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings | 33 | 2.00 | 2007 |
| Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times | 7 | 0.78 | 2007 |
| Symbolic Model Checking of Analog/Mixed-Signal Circuits | 6 | 0.49 | 2007 |
| Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits | 6 | 0.52 | 2007 |
| Verification of Timed Circuits with Failure Directed Abstractions | 8 | 0.53 | 2006 |
| Verification of analog/mixed-signal circuits using labeled hybrid petri nets | 29 | 1.30 | 2006 |
| ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation | 3 | 0.48 | 2006 |
| Effective contraction of timed STGs for decomposition based timed circuit synthesis | 0 | 0.34 | 2006 |
| High level synthesis of timed asynchronous circuits | 9 | 0.58 | 2005 |
| Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation | 0 | 0.34 | 2005 |
| Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits | 6 | 0.48 | 2005 |
| Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets | 12 | 0.71 | 2004 |
| Synthesis of speed independent circuits based on decomposition | 14 | 0.85 | 2004 |
| Modular Synthesis of Timed Circuits using Partial Order Reduction. | 2 | 1.56 | 2002 |
| Automatic Derivation of Timing Constraints by Failure Analysis | 12 | 0.72 | 2002 |
| Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method | 0 | 0.34 | 2002 |
