| Conference Reports | 0 | 0.34 | 2019 |
| GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games | 0 | 0.34 | 2015 |
| A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures | 1 | 0.35 | 2014 |
| A clock control strategy for peak power and RMS current reduction using path clustering | 6 | 0.67 | 2013 |
| Run-time power-gating in caches of GPUs for leakage energy savings | 17 | 0.62 | 2012 |
| A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization | 0 | 0.34 | 2011 |
| Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits | 1 | 0.36 | 2011 |
| Variation-aware multimetric optimization during gate sizing | 0 | 0.34 | 2009 |
| Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty | 2 | 0.38 | 2008 |
| A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing | 0 | 0.34 | 2008 |
| A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors | 7 | 0.58 | 2007 |
| Variation Aware Timing Based Placement Using Fuzzy Programming | 2 | 0.38 | 2007 |
| A microeconomic approach to multi-robot team formation | 3 | 0.41 | 2007 |
| VLSI architecture and chip for combined invisible robust and fragile watermarking | 17 | 0.81 | 2007 |
| A novel approach for variation aware power minimization during gate sizing | 7 | 0.49 | 2006 |
| An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition | 6 | 0.60 | 2006 |
| Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization | 2 | 0.38 | 2006 |
| A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise | 7 | 0.45 | 2006 |
| ILP models for simultaneous energy and transient power minimization during behavioral synthesis | 4 | 0.45 | 2006 |
| A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks | 2 | 0.44 | 2006 |
| A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design | 5 | 0.47 | 2005 |
| Design of a low power image watermarking encoder using dual voltage and frequency | 4 | 0.42 | 2005 |
| A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection | 0 | 0.34 | 2005 |
| Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks | 8 | 0.74 | 2005 |
| Energy-efficient datapath scheduling using multiple voltages and dynamic clocking | 12 | 0.73 | 2005 |
| Stochastic channel-adaptive rate control for wireless video transmission | 6 | 0.52 | 2004 |
| Control and data flow graph extraction for high-level synthesis | 13 | 0.70 | 2004 |
| Cascaded Bayesian inferencing for switching activity estimation with correlated inputs | 9 | 0.72 | 2004 |
| ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis | 9 | 0.54 | 2004 |
| Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis | 0 | 0.34 | 2004 |
| Gate Sizing and Buffer Insertion using Economic Models for Power Optimization | 12 | 0.69 | 2004 |
| A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors | 2 | 0.51 | 2004 |
| A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization | 1 | 0.37 | 2003 |
| Peak Power Minimization Through Datapath Scheduling | 13 | 0.80 | 2003 |
| A game theoretic approach for power optimization during behavioral synthesis | 9 | 0.62 | 2003 |
| Simultaneous peak and average power minimization during datapath scheduling for DSP processors | 4 | 0.49 | 2003 |
| Energy Efficient Scheduling for Datapath Synthesis | 12 | 0.75 | 2003 |
| Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling | 1 | 0.39 | 2003 |
| A low power scheduler using game theory | 4 | 0.43 | 2003 |
| Petri net modeling of gate and interconnect delays for power estimation | 6 | 0.57 | 2003 |
| A Game-Theoretic Approach for Binding in Behavioral Synthesis | 5 | 0.56 | 2003 |
| Power estimation of sequential circuits using hierarchical colored hardware petri net modeling | 0 | 0.34 | 2002 |
| Least-square estimation of average power in digital CMOS circuits | 4 | 0.49 | 2002 |
| A Real Delay Switching Activity Simulator based on Petri net Modeling | 1 | 0.37 | 2002 |
| Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks | 3 | 0.45 | 2002 |
| Average power in digital CMOS circuits using least square estimation | 2 | 0.39 | 2001 |
| Dependency preserving probabilistic modeling of switching activity using bayesian networks | 18 | 1.35 | 2001 |
| Computation of lower bounds for switching activity using decision theory | 4 | 0.55 | 1999 |
| Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages | 1 | 0.36 | 1999 |
| Computing the bivariate Gaussian probability integral. | 0 | 0.34 | 1999 |
