A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology | 5 | 0.66 | 2000 |
A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology | 1 | 0.39 | 2000 |
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply] | 4 | 1.10 | 1997 |
A floating-point divider using redundant binary circuits and an asynchronous clock scheme | 0 | 0.34 | 1997 |
A 1.9-GHz single chip IF transceiver for digital cordless phones | 5 | 2.75 | 1996 |
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture | 34 | 4.26 | 1996 |