Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. | 3 | 0.41 | 2016 |
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. | 1 | 0.35 | 2013 |
High-performance FPGA implementations of the cryptographic hash function JH. | 1 | 0.36 | 2013 |
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. | 1 | 0.39 | 2012 |
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC | 5 | 0.49 | 2012 |
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. | 0 | 0.34 | 2012 |
Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign. | 2 | 0.42 | 2010 |
Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. | 0 | 0.34 | 2010 |