| A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line | 0 | 0.34 | 2021 |
| A 24gb/S/Pin 8gb Gddr6 With A Half-Rate Daisy-Chain-Based Clocking Architecture And Io Circuitry For Low-Noise Operation | 0 | 0.34 | 2021 |
| 23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. | 0 | 0.34 | 2017 |
| A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications | 4 | 0.53 | 2015 |
| Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC | 0 | 0.34 | 2015 |
| Energy/carbon management network for IT equipments | 0 | 0.34 | 2012 |
| A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture | 3 | 0.50 | 2012 |
| A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture | 9 | 0.75 | 2012 |
| Efficient transmit antenna selection for correlated MIMO channels | 4 | 1.12 | 2009 |
| Co-Modeling, Experimental Verification, And Analysis Of Chip-Package Hierarchical Power Distribution Network | 0 | 0.34 | 2008 |
| EA Design Using NGOSS eTOM | 0 | 0.34 | 2007 |
| WBEM-Based SLA management across multi-domain networks for qos-guaranteed DiffServ-over-MPLS provisioning | 1 | 0.37 | 2006 |
