Akira Nagoya - Citegraph

Author Info

Name	Affiliation	Papers
AKIRA NAGOYA	NTT, Commun Sci Labs, Seika, Kyoto 61902, Japan	29
Collaborators	Citations	PageRank
36	141	17.78
Referers	Referees	References
274	277	155

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100277

Publications (29 rows)

Collaborators (36 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual Machines	0	0.34	2018
Network Processor for High-Speed Network and Quick Programming	0	0.34	2007
Dynamically Reconfigurable Logic Lsi: Pca-2	1	0.44	2004
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA	0	0.34	2003
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture.	1	0.79	2003
Solving satisfiability problems using reconfigurable computing	21	1.00	2001
Self-reorganising systems on VLSI circuits	0	0.34	2001
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI	26	2.20	2001
Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture	2	0.47	2001
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation	0	0.34	2000
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology	3	0.70	2000
SPFD: A new method to express functional flexibility	25	1.56	2000
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture	2	0.66	2000
Acceleration of linear block code evaluations using new reconfigurable computing approach	0	0.34	1999
A method for implementing fractal image compression on reconfigurable architecture	0	0.34	1999
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture	1	0.38	1999
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic	0	0.34	1999
An Integrated Approach for Synthesizing LUT Networks	0	0.34	1999
Summation algorithms on constrained reconfigurable meshes	1	0.37	1999
Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation	3	0.47	1999
Restructuring logic representations with easily detectable simple disjunctive decompositions	5	0.57	1998
Soft decision maximum likelihood decoders for binary linear block codes implemented on FPGAs (abstract)	0	0.34	1998
New Methods To Find Optimal Non-Disjoint Bi-Decompositions	8	0.66	1998
Formulation of the Addition-Shift-Sequence Problem and Its Complexity	4	0.65	1997
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables	3	0.58	1997
A hardware/software codesign method for a general purpose reconfigurable co-processor	4	0.56	1997
LUT-based FPGA technology mapping using permissible functions	0	0.34	1996
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization	31	1.65	1995
Multi-Level Optimization for Large Scale ASICS	0	0.34	1990