| A Reconfigurable 74-140Mbps LDPC Decoding System for CCSDS Standard. | 0 | 0.34 | 2021 |
| REDUCED-COMPLEXITY MODULAR POLYNOMIAL MULTIPLICATION FOR R-LWE CRYPTOSYSTEMS | 0 | 0.34 | 2021 |
| Graph-Theoretic Properties of Sub-Graph Entropy | 0 | 0.34 | 2021 |
| Decoding Human Cognitive Control Using Functional Connectivity of Local Field Potentials | 0 | 0.34 | 2021 |
| Spectral Features Based Decoding of Task Engagement: The Role of Theta and High Gamma Bands in Cognitive Control | 0 | 0.34 | 2021 |
| A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks | 0 | 0.34 | 2020 |
| Brain-Inspired Computing: Models and Architectures | 1 | 0.36 | 2020 |
| Classification Of Major Depressive Disorder From Resting-State Fmri | 0 | 0.34 | 2019 |
| MUSE: Minimum Uncertainty and Sample Elimination Based Binary Feature Selection | 1 | 0.35 | 2019 |
| Computing Arithmetic Functions Using Stochastic Logic by Series Expansion | 7 | 0.52 | 2019 |
| Predicting Male Vs. Female From Task-Fmri Brain Connectivity | 0 | 0.34 | 2019 |
| Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs. | 0 | 0.34 | 2019 |
| A Serial Commutator Fast Fourier Architecture for Real-Valued Signals. | 0 | 0.34 | 2018 |
| Canonic FFT flow graphs for real-valued even/odd symmetric inputs. | 2 | 0.40 | 2017 |
| Computing Polynomials by Chemical Reaction Networks. | 0 | 0.34 | 2016 |
| Synthesis of correlated bit streams for stochastic computing | 0 | 0.34 | 2016 |
| Seizure prediction using long-term fragmented intracranial canine and human EEG recordings | 0 | 0.34 | 2016 |
| Optic Disc Boundary and Vessel Origin Segmentation of Fundus Images. | 2 | 0.39 | 2016 |
| Molecular Sensing and Computing Systems. | 2 | 0.37 | 2015 |
| Markov Chain Computations Using Molecular Reactions | 4 | 0.44 | 2015 |
| Joint brain connectivity estimation from diffusion and functional MRI data | 0 | 0.34 | 2015 |
| Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders | 41 | 1.80 | 2014 |
| Robust and low complexity algorithms for seizure detection. | 2 | 0.45 | 2014 |
| Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision | 35 | 1.63 | 2014 |
| Architecture optimizations for BP polar decoders | 27 | 1.53 | 2013 |
| Digital logic with molecular reactions | 3 | 0.51 | 2013 |
| Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits | 0 | 0.34 | 2013 |
| Automated Denoising And Segmentation Of Optical Coherence Tomography Images | 0 | 0.34 | 2013 |
| Comments on "Low-energy CSMT carry generators and binary adders" | 0 | 0.34 | 2013 |
| Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT With Real Datapaths | 13 | 0.95 | 2013 |
| Digital Signal Processing With Molecular Reactions | 10 | 0.82 | 2012 |
| Reducing the number of features for seizure prediction of spectral power in intracranial EEG | 2 | 0.39 | 2012 |
| Session TP8b2: Biomedical signal and image processing. | 0 | 0.34 | 2012 |
| Screening fundus images for diabetic retinopathy | 1 | 0.37 | 2012 |
| Parallel pipelined FFT architectures with reduced number of delays | 4 | 0.49 | 2012 |
| Synchronous sequential computation with molecular reactions | 14 | 1.11 | 2011 |
| Asynchronous computation with molecular reactions | 0 | 0.34 | 2011 |
| Underdetermined blind source separation based on Continuous Density Hidden Markov Models | 0 | 0.34 | 2010 |
| Seizure prediction with spectral power of time/space-differential EEG signals using cost-sensitive support vector machine | 7 | 2.57 | 2010 |
| Low-complexity switch network for reconfigurable LDPC decoders | 22 | 1.01 | 2010 |
| Pulsed-OFDM Modulation for Ultrawideband Communications | 6 | 0.68 | 2009 |
| Low-latency low-complexity architectures for Viterbi decoders | 2 | 0.39 | 2009 |
| A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet | 5 | 0.45 | 2009 |
| Synthesizing sequential register-based computation with biochemistry | 0 | 0.34 | 2009 |
| Minimal complexity low-latency architectures for Viterbi decoders | 1 | 0.39 | 2008 |
| Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders | 6 | 0.68 | 2008 |
| Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes | 3 | 0.49 | 2008 |
| High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform | 28 | 1.11 | 2008 |
| High-Throughput VLSI Architecture for FFT Computation | 25 | 2.03 | 2007 |
| High-Speed Architecture Design of Tomlinson–Harashima Precoders | 13 | 1.11 | 2007 |
