| A study of Thread Level Parallelism on mobile devices | 8 | 0.55 | 2014 |
| Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". | 73 | 4.39 | 2011 |
| Evolution of thread-level parallelism in desktop applications | 51 | 3.13 | 2010 |
| Life on the Treadmill | 0 | 0.34 | 2009 |
| Addressing design margins through error-tolerant circuits | 5 | 0.45 | 2009 |
| PicoServer: Using 3D stacking technology to build energy efficient servers | 18 | 1.31 | 2008 |
| Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor | 1 | 0.35 | 2008 |
| Introduction to embedded systems week 2006 special issue | 0 | 0.34 | 2008 |
| The State of ESL Design [Roundtable] | 1 | 0.37 | 2008 |
| Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008 | 1 | 0.36 | 2008 |
| Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006 | 40 | 3.81 | 2006 |
| Design and Implementation of Turbo Decoders for Software Defined Radio | 18 | 1.61 | 2006 |
| Topic 18: Embedded Parallel Systems | 0 | 0.34 | 2006 |
| Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems | 1 | 0.38 | 2006 |
| An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors | 88 | 3.10 | 2005 |
| Making typical silicon matter with Razor | 83 | 5.75 | 2004 |
| Circuit and microarchitectural techniques for reducing cache leakage power | 75 | 10.18 | 2004 |
| IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling | 27 | 1.83 | 2004 |
| Extended dynamic voltage scaling for low power design. | 1 | 0.63 | 2004 |
| Leakage Current: Moore's Law Meets Static Power | 358 | 17.14 | 2003 |
| Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads | 232 | 12.53 | 2002 |
| Automatic performance setting for dynamic voltage scaling | 119 | 22.95 | 2002 |
| Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction | 91 | 6.51 | 2002 |
| Drowsy caches: simple techniques for reducing leakage power | 365 | 26.83 | 2002 |
| Leakage Current Reduction in VLSI Systems | 6 | 0.54 | 2002 |
| Vertigo: automatic performance-setting for Linux | 92 | 15.60 | 2002 |
| A high level simulator integrated with the Mirv compiler | 0 | 0.34 | 1999 |
