| Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation | 0 | 0.34 | 2021 |
| Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning | 0 | 0.34 | 2021 |
| Skip-Connected Self-Recurrent Spiking Neural Networks With Joint Intrinsic Parameter And Synaptic Weight Training | 0 | 0.34 | 2021 |
| Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal Circuits | 0 | 0.34 | 2021 |
| Sliding mode control of neural networks via continuous or periodic sampling event-triggering algorithm. | 5 | 0.39 | 2020 |
| A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition | 1 | 0.43 | 2020 |
| Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns | 0 | 0.34 | 2020 |
| Rethinking the performance comparison between SNNS and ANNS. | 10 | 0.46 | 2020 |
| Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal Circuits | 0 | 0.34 | 2019 |
| Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-chip Voltage Regulation | 0 | 0.34 | 2019 |
| Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation | 1 | 0.37 | 2019 |
| Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint. | 1 | 0.38 | 2018 |
| Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage. | 0 | 0.34 | 2018 |
| Simulation of a Multidimensional Input Quantum Perceptron. | 1 | 0.34 | 2018 |
| Efficient Two-Step Adversarial Defense for Deep Neural Networks. | 0 | 0.34 | 2018 |
| Area-efficient and low-power face-to-face-bonded 3D liquid state machine design. | 0 | 0.34 | 2018 |
| Performance and robustness of bio-inspired digital liquid state machines: A case study of speech recognition. | 0 | 0.34 | 2017 |
| Multiharmonic Small-Signal Modeling of Low-Power PWM DC-DC Converters. | 0 | 0.34 | 2017 |
| Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM | 1 | 0.40 | 2016 |
| Using Presilicon Knowledge to Excite Nonlinear Failure Modes in Large Mixed-Signal Circuits. | 0 | 0.34 | 2016 |
| Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration. | 7 | 0.50 | 2016 |
| SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processors | 6 | 0.48 | 2016 |
| Robust and Efficient Transistor-level Envelope-Following Analysis of PWM/PFM/PSM DC-DC Converters | 0 | 0.34 | 2016 |
| Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating | 0 | 0.34 | 2015 |
| Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing | 6 | 0.45 | 2015 |
| A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing | 5 | 0.44 | 2015 |
| Reachability Analysis Using Extremal Rates. | 0 | 0.34 | 2015 |
| Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design | 5 | 0.45 | 2015 |
| Circuit design and exponential stabilization of memristive neural networks. | 75 | 1.77 | 2015 |
| FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. | 1 | 0.36 | 2014 |
| Approximate property checking of mixed-signal circuits | 3 | 0.46 | 2014 |
| Transformations for throughput optimization in high-level synthesis (abstract only) | 2 | 0.43 | 2014 |
| SBAC: a statistics based cache bypassing method for asymmetric-access caches | 6 | 0.43 | 2014 |
| A model for array-based approximate arithmetic computing with application to multiplier and squarer design | 6 | 0.53 | 2014 |
| Simulation-Assisted Formal Verification of Nonlinear Mixed-Signal Circuits With Bayesian Inference Guidance | 5 | 0.44 | 2013 |
| A Hierarchical Architectural Framework for Reconfigurable Logic Computing | 0 | 0.34 | 2013 |
| Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis | 7 | 0.58 | 2013 |
| IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications | 2 | 0.41 | 2013 |
| A 0.38 V near/sub-VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process | 1 | 0.36 | 2013 |
| The emergence of abnormal hypersynchronization in the anatomical structural network of human brain. | 7 | 0.70 | 2013 |
| Load-aware stochastic feedback control for DVFS with tight performance guarantee | 0 | 0.34 | 2012 |
| Memory partitioning and scheduling co-optimization in behavioral synthesis | 16 | 0.95 | 2012 |
| Quantifying dynamic stability of genetic memory circuits. | 2 | 0.53 | 2012 |
| Design analysis of IC power delivery | 0 | 0.34 | 2012 |
| Design and optimization of power gating for DVFS applications | 1 | 0.35 | 2012 |
| Linking brain behavior to underlying cellular mechanisms via large-scale brain modeling and simulation | 2 | 0.39 | 2012 |
| Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems | 0 | 0.34 | 2012 |
| Locality-Driven Parallel Static Analysis for Power Delivery Networks | 8 | 0.53 | 2011 |
| Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories | 87 | 7.96 | 2011 |
| High effective-resolution built-in jitter characterization with quantization noise shaping | 0 | 0.34 | 2011 |
