A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition | 0 | 0.34 | 2019 |
Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA. | 0 | 0.34 | 2019 |
A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization. | 0 | 0.34 | 2019 |
A technology mapper for depth-constrained FPGA logic cells | 1 | 0.38 | 2015 |
A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter | 0 | 0.34 | 2015 |
A semi-supervised modeling approach for performance characterization of FPGA architectures | 0 | 0.34 | 2014 |