Linxiao Shen - Citegraph

Author Info

Name	Affiliation	Papers
LINXIAO SHEN	Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA	30
Collaborators	Citations	PageRank
111	23	10.68
Referers	Referees	References
102	654	188

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100654

Publications (30 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms	0	0.34	2022
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.	0	0.34	2022
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques	0	0.34	2022
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-<italic>π</italic> Network in 40-nm CMOS	0	0.34	2021
A 79db-Sndr 167db-Fom Bandpass Delta Sigma Adc Combining N-Path Filter With Noise-Shaping Sar	0	0.34	2021
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network	1	0.34	2021
A Software-Defined Always-On System With 57–75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC	3	0.39	2021
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array	1	0.36	2021
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR	0	0.34	2021
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems	1	0.36	2021
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC	0	0.34	2020
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW	0	0.34	2020
16.5 A 13b 0.005mm(2) 40ms/S Sar Adc With Kt/C Noise Cancellation	0	0.34	2020
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning	1	0.36	2020
Gcn-Rl Circuit Designer: Transferable Transistor Sizing With Graph Neural Networks And Reinforcement Learning	1	0.35	2020
S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity	1	0.37	2020
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter	0	0.34	2020
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier	2	0.37	2020
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier	1	0.35	2020
A 13-bit 0.005-mm<sup>2</sup> 40-MS/s SAR ADC With kT/C Noise Cancellation	0	0.34	2020
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF	0	0.34	2019
A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure	0	0.34	2019
Device Layer-Aware Analytical Placement for Analog Circuits.	2	0.42	2019
A Two-Step ADC With a Continuous-Time SAR-Based First Stage	2	0.37	2019
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.	0	0.34	2019
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout	6	0.49	2019
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique	0	0.34	2019
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS	1	0.41	2018
A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor.	0	0.34	2018
Nfc-Enabled, Tattoo-Like Stretchable Biosensor Manufactured By "Cut-And-Paste" Method	0	0.34	2017