| Boost-RS: boosted embeddings for recommender systems and its application to enzyme-substrate interaction prediction | 0 | 0.34 | 2022 |
| Workshop on Microbiomics, Metagenomics, and Metabolomics | 0 | 0.34 | 2019 |
| Towards the Design of Matrix Metalloproteinases (MMP) Antibody Sequences | 0 | 0.34 | 2017 |
| Pathway Enrichment Analysis for Untargeted Metabolomics | 0 | 0.34 | 2017 |
| A Workshop on Microbiomics, Metagenomics, and Metabolomics | 0 | 0.34 | 2017 |
| A Tool for Predicting the Dark Side of Enzymes | 0 | 0.34 | 2017 |
| ProSol DB: A Protein Solubility Database | 0 | 0.34 | 2017 |
| An Advanced Workflow for Metabolite Annotation | 0 | 0.34 | 2017 |
| Steven P. Levitan (1950-2016). | 0 | 0.34 | 2016 |
| PreProPath: An Uncertainty-Aware Algorithm for Identifying Predictable Profitable Pathways in Biochemical Networks. | 1 | 0.36 | 2015 |
| Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits | 0 | 0.34 | 2015 |
| PROXIMAL: a method for Prediction of Xenobiotic Metabolism | 1 | 0.48 | 2015 |
| Discovery of substrate cycles in large scale metabolic networks using hierarchical modularity. | 1 | 0.38 | 2015 |
| Guest Editors' Introduction: Highlights of the 50th DAC. | 0 | 0.34 | 2014 |
| Decomposing Biochemical Networks Into Elementary Flux Modes Using Graph Traversal | 2 | 0.40 | 2013 |
| MC3: a steady-state model and constraint consistency checker for biochemical networks. | 3 | 0.34 | 2013 |
| Probabilistic strain optimization under constraint uncertainty. | 3 | 0.34 | 2013 |
| New topic session 2B: Why (Re-)Designing Biology is ∗Slightly∗ more challenging than designing electronics | 0 | 0.34 | 2013 |
| Abstraction of Kinetic Models For Biochemical Networks | 0 | 0.34 | 2013 |
| Guest Editors' Introduction: Synthetic Biology. | 0 | 0.34 | 2012 |
| Genetic/bio design automation for (re-)engineering biological systems | 1 | 0.37 | 2012 |
| Design Automation for Synthetic Biological Systems. | 8 | 0.73 | 2012 |
| Metabolic Flux-Based Modularity using Shortest Retroactive distances. | 3 | 0.39 | 2012 |
| Identification of Biochemical Network Modules Based on Shortest Retroactive Distances. | 5 | 0.50 | 2011 |
| Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies | 26 | 1.37 | 2011 |
| Early estimation of TSV area for power delivery in 3-D integrated circuits. | 2 | 0.38 | 2010 |
| Fast, accurate a priori routing delay estimation | 0 | 0.34 | 2010 |
| Joint DAC/IWBDA special session engineering biology: fundamentals and applications | 0 | 0.34 | 2010 |
| Evolving soft robotic locomotion in PhysX | 19 | 1.26 | 2009 |
| System-Level Comparison Of Power Delivery Design For 2d And 3d Ics | 18 | 1.09 | 2009 |
| An algorithm for identifying dominant-edge metabolic pathways | 3 | 0.47 | 2009 |
| Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs | 12 | 1.38 | 2009 |
| Electro-thermal analysis of multi-fin devices | 8 | 1.46 | 2008 |
| METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs | 1 | 0.48 | 2006 |
| Gate sizing: finFETs vs 32nm bulk MOSFETs | 33 | 2.29 | 2006 |
| 2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA | 133 | 18.33 | 2006 |
| A transaction-based unified architecture for simulation and emulation | 4 | 0.63 | 2005 |
| First CADathlon Programming Contest held at 2002 ICCAD | 0 | 0.34 | 2003 |
| Guest Editors' Introduction: On-Chip Power Distribution Networks | 0 | 0.34 | 2003 |
| Static timing analysis for level-clocked circuits in the presence of crosstalk | 1 | 0.35 | 2003 |
| Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading | 2 | 0.36 | 2003 |
| Optimal buffered routing path constructions for single and multiple clock domain systems | 30 | 1.55 | 2002 |
| Robust SAT-Based Search Algorithm for Leakage Power Reduction | 24 | 1.63 | 2002 |
| A transaction-based unified simulation/emulation architecture for functional verification | 16 | 2.48 | 2001 |
| Critical path analysis using a dynamically bounded delay model | 16 | 0.83 | 2000 |
| Regularity extraction via clan-based structural circuit decomposition | 6 | 0.56 | 1999 |
| Fine grain incremental rescheduling via architectural retiming | 7 | 0.65 | 1998 |
| Using precomputation in architecture and logic resynthesis | 6 | 0.63 | 1998 |
| Architectural retiming: pipelining latency-constrained circuits | 31 | 2.20 | 1996 |
| The chaos router chip: design and implementation of an adaptive router | 11 | 18.83 | 1993 |
