Name
Affiliation
Papers
FARZAN FALLAH
Fujitsu Laboratories of America, San Jose, CA
44
Collaborators
Citations 
PageRank 
39
557
43.73
Referers 
Referees 
References 
1061
706
453
Search Limit
1001000
Title
Citations
PageRank
Year
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection110.662014
Overcoming post-silicon validation challenges through quick error detection (QED)30.382013
Combinational Logic Design Using Six-Terminal NEM Relays151.102013
Quick detection of difficult bugs for effective post-silicon validation180.702012
Low-power fanout optimization using multi threshold voltages and multi channel lengths00.342009
Xquasher: a tool for efficient computation of multiple linear expressions40.422009
Charge Recycling in Power-Gated CMOS Circuits120.882008
Sizing and placement of charge recycling transistors in MTCMOS circuits10.372007
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design251.482007
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems50.772007
Low-leakage SRAM Design with Dual V_t Transistors10.372006
Charge recycling in MTCMOS circuits: concept and analysis130.952006
Low-power fanout optimization using MTCMOS and multi-Vt techniques60.542006
Optimizing high speed arithmetic circuits using three-term extraction50.552006
Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment110.862006
Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions141.042005
Low-power fanout optimization using multiple threshold voltage inverters30.412005
Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits10.372005
A way memoization technique for reducing power consumption of caches in application specific integrated processors80.552005
A cache-defect-aware code placement algorithm for improving the performance of processors100.702005
An effective power mode transition technique in MTCMOS circuits261.792005
Standby And Active Leakage Current Control And Minimization In Cmos Vlsi Circuits653.552005
Energy Efficient Hardware Synthesis of Polynomial Expressions60.542005
A non-uniform cache architecture for low power system design130.652005
Transition reduction in memory buses using sector-based encoding techniques60.492004
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis70.662004
Leakage current reduction in CMOS VLSI circuits by input vector control673.932004
Factoring and eliminating common subexpressions in polynomial expressions170.972004
Leakage current reduction in sequential circuits by modifying the scan chains20.622003
Event-driven observability enhanced coverage analysis of C programs for functional validation20.402003
Precomputation-based Guarding for Dynamic and Leakage Power Reduction91.072003
BEAM: bus encoding based on instruction-set-aware memories00.342003
Reducing transitions on memory buses using sector-based encoding technique30.452002
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits00.342002
A Class of Irredundant Encoding Techniques for Reducing Bus Power30.432002
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2242.282002
ALBORZ: Address Level Bus Power Optimization50.522002
Binary time-frame expansion40.472002
Functional vector generation for HDL models using linearprogramming and Boolean satisfiability111.102001
Occom - Efficient Computation Of Observability-Based Code Coverage Metrics For Functional Verification30.512001
Observability enhanced coverage analysis of C programs for functional validation00.342001
Solving covering problems using LPR-based lower bounds60.922000
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage453.771999
Functional vector generation for HDL models using linear programming and 3-satisfiability674.181998