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RAKESH KUMAR
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Name
Affiliation
Papers
RAKESH KUMAR
Univ Politecn Cataluna, Dept Comp Architecture, Barcelona, Spain
10
Collaborators
Citations
PageRank
15
22
3.62
Referers
Referees
References
83
266
108
Search Limit
100
266
Publications (10 rows)
Collaborators (15 rows)
Referers (83 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Fiforder Microarchitecture: Ready-Aware Instruction Scheduling For Ooo Processors
0
0.34
2019
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
4
0.38
2019
Blasting through the Front-End Bottleneck with Shotgun.
3
0.37
2018
Boomerang: A Metadata-Free Architecture for Control Flow Delivery
6
0.40
2017
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment
0
0.34
2016
Quantitative characterization of the software layer of a HW/SW co-designed processor
0
0.34
2016
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment.
2
0.36
2014
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment
2
0.36
2013
Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment
2
0.36
2013
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment
3
0.38
2013
1