| GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent | 5 | 0.39 | 2021 |
| Aging Gracefully with Approximation | 1 | 0.43 | 2019 |
| Cell division - weight bit-width reduction technique for convolutional neural network hardware accelerators. | 0 | 0.34 | 2019 |
| An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. | 1 | 0.36 | 2018 |
| Tapered-Ratio Compression for Residual Network | 0 | 0.34 | 2018 |
| Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands. | 0 | 0.34 | 2018 |
| Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation. | 1 | 0.36 | 2018 |
| ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator. | 4 | 0.40 | 2018 |
| Architectures and algorithms for user customization of CNNs. | 1 | 0.35 | 2018 |
| Network Recasting: A Universal Method for Network Architecture Transformation | 0 | 0.34 | 2018 |
| Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks | 0 | 0.34 | 2018 |
| FPGA implementation of convolutional neural network based on stochastic computing | 1 | 0.35 | 2017 |
| A new stochastic mutiplier for deep neural networks | 0 | 0.34 | 2017 |
| Autonomic Diffusive Load Balancing On Many-Core Architecture Using Simulated Annealing | 0 | 0.34 | 2017 |
| ExtraV: boosting graph processing near storage with a coherent accelerator | 7 | 0.44 | 2017 |
| Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch. | 2 | 0.37 | 2017 |
| Optimal mapping of program overlays onto many-core platforms with limited memory capacity. | 0 | 0.34 | 2017 |
| Design space exploration of FPGA accelerators for convolutional neural networks. | 4 | 0.45 | 2017 |
| Adaptive delay monitoring for wide voltage-range operation | 1 | 0.37 | 2016 |
| Exploration of trade-offs in the design of volatile STT-RAM cache. | 1 | 0.35 | 2016 |
| Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. | 6 | 0.41 | 2016 |
| Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. | 29 | 1.45 | 2016 |
| Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip | 4 | 0.43 | 2016 |
| A new approach to binarizing neural networks | 0 | 0.34 | 2016 |
| Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture | 11 | 0.62 | 2016 |
| Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching | 6 | 0.45 | 2016 |
| PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture | 116 | 2.35 | 2015 |
| THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures | 4 | 0.38 | 2015 |
| DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture | 37 | 1.27 | 2014 |
| Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12) | 0 | 0.34 | 2014 |
| Configurable range memory for effective data reuse on programmable accelerators | 0 | 0.34 | 2014 |
| Tree-Mesh Heterogeneous Topology for Low-Latency NoC. | 4 | 0.51 | 2014 |
| Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture | 3 | 0.38 | 2014 |
| A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections | 6 | 0.44 | 2013 |
| Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA | 12 | 0.63 | 2013 |
| CPU-based speed acceleration techniques for shear warp volume rendering | 2 | 0.50 | 2013 |
| Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches | 4 | 0.39 | 2013 |
| Deflection routing in 3D network-on-chip with limited vertical bandwidth | 4 | 0.39 | 2013 |
| Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth | 0 | 0.34 | 2013 |
| Lower-bits cache for low power STT-RAM caches | 14 | 0.77 | 2012 |
| Guest Editorial New Interconnect Technologies in On-Chip Communication | 0 | 0.34 | 2012 |
| Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips | 4 | 0.44 | 2012 |
| Exploiting New Interconnect Technologies in On-Chip Communication | 9 | 0.54 | 2012 |
| An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors | 2 | 0.37 | 2011 |
| Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane. | 0 | 0.34 | 2011 |
| Simulated annealing-based diffusive load balancing on many-core SoC | 1 | 0.37 | 2011 |
| Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures | 17 | 0.75 | 2011 |
| 3D network-on-chip with wireless links through inductive coupling | 4 | 0.41 | 2011 |
| Coarse-Grained Reconfigurable Array: Architecture and Application Mapping. | 14 | 0.71 | 2011 |
| CRM: Configurable Range Memory for Fast Reconfigurable Computing | 2 | 0.47 | 2011 |
