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| Gate-level modelling and verification of asynchronous circuits using CSPM and FDR | 2 | 0.39 | 2007 |
| Controllable Delay-Insensitive Processes | 2 | 0.40 | 2007 |
| Asynchronous Packet-Switching for Networks-on-Chip | 0 | 0.34 | 2006 |
| Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments | 4 | 0.44 | 2006 |
| Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation | 1 | 0.35 | 2005 |
| Models for data-flow sequential processes | 2 | 0.46 | 2004 |
| Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench | 7 | 0.59 | 2004 |
| Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis | 4 | 0.42 | 2004 |
| An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits | 4 | 0.51 | 2003 |
| A Programming Approach to the Design of Asynchronous Logic Blocks | 11 | 0.75 | 2002 |
| Optimal Two-Level Delay - Insensitive Implementation of Logic Functions | 1 | 0.37 | 2002 |
| Delay-insensitive interface specification and synthesis | 6 | 0.55 | 2000 |
| Modeling and design of asynchronous circuits | 17 | 1.45 | 1999 |
| Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review) | 0 | 0.34 | 1998 |
| Formal Derivation of a Loadable Asynchronous Counter | 2 | 0.48 | 1998 |
| The Use of SI-Algebra in the Design of Sequencer Circuits | 3 | 0.43 | 1997 |
| CMOS design of the tree arbiter element | 20 | 2.38 | 1996 |
| Some limitations to speed-independence in asynchronous circuits. | 2 | 0.46 | 1996 |
| Sequencer circuits for VLSI programming | 8 | 1.02 | 1995 |
| Specifying distributed CICS in Z: Accessing local and remote resources | 4 | 0.46 | 1994 |
| Implementing a Stack as a Delay-insensitive Circuit | 2 | 0.47 | 1993 |
| Normal Form in a Delay-Insensitive Algebra | 5 | 0.73 | 1993 |
| Receptive process theory | 48 | 4.44 | 1992 |
| High-Level Design of an Asynchronous Packet-Routing Chip | 4 | 0.98 | 1992 |
| A Theory Of Synchrony And Asynchrony | 35 | 3.32 | 1990 |
| Delay-insensitive circuits: an algebraic approach to their design | 17 | 2.36 | 1990 |
| An Algebra for Delay-Insensitive Circuits | 18 | 2.76 | 1990 |
| A State-Based Approach to Communicating Processes | 68 | 6.27 | 1988 |
| Functional programming with side-effects | 5 | 0.99 | 1986 |
