| MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs | 0 | 0.34 | 2022 |
| Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency. | 0 | 0.34 | 2018 |
| Softmc: Practical Dram Characterization Using An Fpga-Based Infrastructure | 0 | 0.34 | 2018 |
| Opcode vector: An efficient scheme to detect soft errors in instructions. | 0 | 0.34 | 2018 |
| SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies | 25 | 0.53 | 2017 |
| GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping. | 12 | 0.48 | 2017 |
| URFA-Update based register file architecture with partial register write for energy efficiency. | 0 | 0.34 | 2016 |
| Error recovery through partial value similarity | 0 | 0.34 | 2016 |
| GateKeeper: Enabling Fast Pre-Alignment in DNA Short Read Mapping with a New Streaming Accelerator Architecture. | 0 | 0.34 | 2016 |
| Using value similarity of registers for soft error mitigation | 2 | 0.39 | 2015 |
| GPU based parallel image processing library for embedded systems | 0 | 0.34 | 2014 |
| Exploiting processor features to implement error detection in reduced precision matrix multiplications | 1 | 0.35 | 2014 |
| Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values | 0 | 0.34 | 2013 |
| Exploiting replicated checkpoints for soft error detection and correction | 0 | 0.34 | 2013 |
| Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration | 1 | 0.44 | 2012 |
| Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators | 0 | 0.34 | 2012 |
| Using content-aware bitcells to reduce static energy dissipation | 1 | 0.35 | 2011 |
| Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands | 0 | 0.34 | 2010 |
| Reducing Soft Errors through Operand Width Aware Policies | 8 | 0.55 | 2009 |
| Reducing parity generation latency through input value aware circuits | 2 | 0.38 | 2009 |
| Modifying the Data-Holding Components of the Microprocessors for Energy Efficiency | 1 | 0.36 | 2009 |
| Refueling: Preventing Wire Degradation due to Electromigration | 9 | 0.78 | 2008 |
| Using Tag-Match Comparators for Detecting Soft Errors | 3 | 0.38 | 2007 |
| Fuse: A Technique to Anticipate Failures due to Degradation in ALUs | 3 | 0.39 | 2007 |
| Exploiting Narrow Values for Soft Error Tolerance | 25 | 0.93 | 2006 |
| Early Register Deallocation Mechanisms Using Checkpointed Register Files | 14 | 0.63 | 2006 |
| Impact of Parameter Variations on Circuits and Microarchitecture | 52 | 1.80 | 2006 |
| Empowering a helper cluster through data-width aware instruction selection policies | 1 | 0.35 | 2006 |
| Instruction packing: Toward fast and energy-efficient instruction scheduling | 5 | 0.44 | 2006 |
| Power-Efficient Wakeup Tag Broadcast | 6 | 0.52 | 2005 |
| Instruction packing: reducing power and delay of the dynamic scheduling logic | 19 | 0.66 | 2005 |
| Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization | 24 | 1.80 | 2004 |
| Defining Wakeup Width for Efficient Dynamic Scheduling | 10 | 0.50 | 2004 |
| Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure | 57 | 1.76 | 2004 |
| Increasing Processor Performance Through Early Register Release | 34 | 1.12 | 2004 |
| Power efficient comparators for long arguments in superscalar processors | 2 | 0.38 | 2003 |
| Distributed Reorder Buffer Schemes for Low Power | 4 | 0.42 | 2003 |
| Energy-efficient issue queue design | 25 | 0.87 | 2003 |
| Reducing Datapath Energy through the Isolation of Short-Lived Operands | 15 | 0.71 | 2003 |
| Reducing reorder buffer complexity through selective operand caching | 63 | 3.49 | 2003 |
