| LwMLA-NET: A Lightweight Multi-Level Attention-Based NETwork for Segmentation of COVID-19 Lungs Abnormalities From CT Images | 0 | 0.34 | 2022 |
| Exploring Spike-Based Learning for Neuromorphic Computing - Prospects and Perspectives. | 0 | 0.34 | 2021 |
| DCT-SNN - Using DCT to Distribute Spatial Information over Time for Low-Latency Spiking Neural Networks. | 0 | 0.34 | 2021 |
| RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks | 1 | 0.35 | 2020 |
| A Low Effort Approach to Structured CNN Design Using PCA. | 1 | 0.37 | 2020 |
| Patch-based system for Classification of Breast Histology images using deep learning. | 7 | 0.52 | 2019 |
| Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting. | 0 | 0.34 | 2019 |
| Adaptive accelerated aging for 28 nm HKMG technology. | 0 | 0.34 | 2018 |
| Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets. | 1 | 0.48 | 2017 |
| Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing. | 3 | 0.42 | 2017 |
| Stochastic Switching Of She-Mtj As A Natural Annealer For Efficient Combinatorial Optimization | 0 | 0.34 | 2017 |
| Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper). | 0 | 0.34 | 2017 |
| Fast, low power evaluation of elementary functions using radial basis function networks. | 0 | 0.34 | 2017 |
| Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction. | 0 | 0.34 | 2016 |
| Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. | 7 | 0.50 | 2016 |
| Ultra-thin dielectric breakdown in devices and circuits: A brief review. | 0 | 0.34 | 2015 |
| Exploring Spin-Transfer-Torque Devices for Logic Applications | 5 | 0.51 | 2015 |
| Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter | 3 | 0.45 | 2015 |
| Approximate computing and the quest for computing efficiency | 49 | 1.51 | 2015 |
| Self-Organizing Aerial Mesh Networks For Emergency Communication | 10 | 0.71 | 2014 |
| Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells | 27 | 1.41 | 2014 |
| Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices | 10 | 0.85 | 2013 |
| Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs | 1 | 0.39 | 2013 |
| Write-optimized reliable design of STT MRAM | 32 | 1.46 | 2012 |
| Variation-aware and self-healing design methodology for a system-on-chip | 1 | 0.37 | 2012 |
| IMPACT: imprecise adders for low-power approximate computing | 147 | 6.22 | 2011 |
| Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking | 3 | 0.43 | 2011 |
| A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array | 5 | 0.50 | 2011 |
| CRP: A Routing Protocol for Cognitive Radio Ad Hoc Networks | 109 | 3.80 | 2011 |
| Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching | 1 | 0.35 | 2010 |
| Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis | 8 | 0.62 | 2010 |
| Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering | 5 | 0.58 | 2010 |
| Coping with Variations through System-Level Design | 2 | 0.40 | 2009 |
| Read/Access-Preferred (Reap) Sram - Architecture-Aware Bit Cell Design For Improved Yield And Lower V-Min | 0 | 0.34 | 2009 |
| Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies | 3 | 0.52 | 2009 |
| A Low-Power SRAM Using Bit-Line Charge-Recycling | 17 | 1.19 | 2008 |
| Tutorial: SoC Power Management Verification and Testing Issues | 1 | 0.36 | 2008 |
| O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors | 4 | 0.54 | 2008 |
| Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement | 22 | 6.63 | 2008 |
| Process variation tolerant SRAM array for ultra low voltage applications | 25 | 1.91 | 2008 |
| Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices | 1 | 0.44 | 2007 |
| Adaptive Supply Voltage For Low-Power Ripple-Carry And Carry-Select Adders | 0 | 0.34 | 2007 |
| Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis | 66 | 4.93 | 2007 |
| A High Performance, Scalable Multiplexed Keeper Technique | 1 | 0.37 | 2007 |
| Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQ measurement | 7 | 0.95 | 2007 |
| A low-power SRAM using bit-line charge-recycling technique | 2 | 0.53 | 2007 |
| Finfet Sram: Optimizing Silicon Fin Thickness And Fin Ratio To Improve Stability At Iso Area | 5 | 0.97 | 2007 |
| Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor | 1 | 0.49 | 2006 |
| Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network | 0 | 0.34 | 2006 |
| Modeling and Analysis of Leakage Currents in Double-Gate Technologies | 6 | 1.05 | 2006 |
