HoL-Blocking Avoidance Routing Algorithms in Direct Topologies | 2 | 0.36 | 2014 |
Hardware-based generation of independent subtraces of instructions in clustered processors | 0 | 0.34 | 2013 |
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions | 0 | 0.34 | 2012 |
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading | 6 | 0.72 | 2009 |
Voltage transient detection and induction for debug and test | 25 | 2.47 | 2009 |
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures | 1 | 0.35 | 2008 |
Improving routing performance in Myrinet networks | 30 | 2.31 | 2000 |