Chao Wang - Citegraph

Author Info

Name	Affiliation	Papers
CHAO WANG	Center for Signal Processing, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore and Digital Signal Processing Lab, School of Electrical and Electronic En ...	49
Collaborators	Citations	PageRank
130	64	18.45
Referers	Referees	References
218	549	209

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100549

Publications (49 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Automatic pulmonary auscultation grading diagnosis of Coronavirus Disease 2019 in China with artificial intelligence algorithms: A cohort study	0	0.34	2022
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions	0	0.34	2021
UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression	0	0.34	2021
Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach	1	0.35	2021
Corrigendum to “Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor” [Microelectron. J. 103C (2020) 104844]	0	0.34	2021
Efficient Design of Spiking Neural Network With STDP Learning Based on Fast CORDIC	1	0.35	2021
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron	0	0.34	2021
WooKong: A Ubiquitous Accelerator for Recommendation Algorithms with Custom Instruction Sets on FPGA	0	0.34	2020
A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices.	1	0.36	2020
OctCNN: An Energy-Efficient FPGA Accelerator for CNNs using Octave Convolution Algorithm	0	0.34	2020
Addressing Irregularity in Sparse Neural Networks Through a Cooperative Software/Hardware Approach	1	0.34	2020
Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor	0	0.34	2020
Drama - A high efficient neural network accelerator on FPGA using dynamic reconfiguration - work-in-progress.	0	0.34	2019
FPNet: Customized Convolutional Neural Network for FPGA Platforms	0	0.34	2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells	0	0.34	2019
DCW: A Reactive and Predictable Programming Framework for LET-Based Distributed Real-Time Systems	0	0.34	2019
A Survey of FPGA Based Deep Learning Accelerators: Challenges and Opportunities.	0	0.34	2019
Design Exploration of Multi-FPGAs for Accelerating Deep Learning	0	0.34	2019
A large-scale in-memory computing for deep neural network with trained quantization.	0	0.34	2019
WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress)	0	0.34	2018
RTMUSRT: a real-time testbed for empirically comparing real-time multicore schedulers: work-in-progress.	0	0.34	2018
Domino: Graph Processing Services on Energy-Efficient Hardware Accelerator	1	0.36	2018
Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only).	0	0.34	2018
Furion: alleviating overheads for deep learning framework on single machine (work-in-progress)	0	0.34	2018
Supporting Predictable Servant-Based Execution Model on Multicore Platforms.	0	0.34	2018
A 1-V to 0.29-V sub-100-pJ/operation ultra-low power fast-convergence CORDIC processor in 0.18-μm CMOS.	0	0.34	2018
Exploiting Aperiodic Server to Improve Aperiodic Responsiveness for LET-Based Real-Time Systems	0	0.34	2017
Circuits and Systems for Wireless Sensing.	0	0.34	2017
Clockwerk: A Predictable and Efficient Extension of Logical Execution Time Model	1	0.35	2017
Tickwerk: Design of a LET-Based SoC for Temporal Programming.	0	0.34	2017
Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network	0	0.34	2017
A Predictable Servant-Based Execution Model For Safety-Critical Systems	0	0.34	2017
A Time-Aware Programming Framework for Constructing Predictable Real-Time Systems	0	0.34	2017
A High-Performance Accelerator for Large-Scale Convolutional Neural Networks	0	0.34	2017
Building a Game Benchmark for Cooperative CPU-GPU with Pseudo User-Interaction	0	0.34	2017
Genserv: Genome Sequencing Services On Scalable Energy Efficient Accelerators	1	0.44	2017
A 0.18µm, 0.6V, 83.5µW integer DCT processor for neural signal applications	0	0.34	2016
A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring	0	0.34	2016
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems	9	0.55	2015
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage	15	0.75	2015
Fast and energy-efficient low-voltage level shifters.	2	0.42	2015
Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications	10	0.68	2015
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing	2	0.39	2015
A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation	0	0.34	2014
Coordinate page allocation and thread group for improving main memory power efficiency	7	0.47	2013
Efficient algorithm and architecture of critical-band transform for low-power speech applications	0	0.34	2007
Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform	10	0.73	2007
Efficient Vlsi Architecture Of Lifting-Based Wavelet Packet Transform For Audio And Speech Applications	0	0.34	2006
An improved critical-band transform processor for speech applications	2	0.41	2004