| Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES | 1 | 0.35 | 2019 |
| High-Level Synthesis with Timing-Sensitive Information Flow Enforcement | 0 | 0.34 | 2018 |
| NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. | 2 | 0.41 | 2017 |
| FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. | 0 | 0.34 | 2016 |
| A technology mapper for depth-constrained FPGA logic cells | 1 | 0.38 | 2015 |
| Exploring architecture parameters for dual-output LUT based FPGAs | 0 | 0.34 | 2014 |
