Name
Affiliation
Papers
ARIJIT RAYCHOWDHURY
Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA
80
Collaborators
Citations 
PageRank 
178
284
48.04
Referers 
Referees 
References 
767
864
270
Search Limit
100864
Title
Citations
PageRank
Year
An End-to-End Spiking Neural Network Platform for Edge Robotics: From Event-Cameras to Central Pattern Generation00.342022
Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation00.342022
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge00.342022
An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems00.342022
RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning00.342022
FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems00.342022
Improving compute in-memory ECC reliability with successive correction00.342022
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems00.342022
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory20.652022
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.00.342022
Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity00.342022
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller00.342022
Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses00.342022
A Practical Design-Space Analysis of Compute-in-Memory With SRAM00.342022
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm00.342022
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads00.342021
A 40nm 64kb 56.67tops/W Read-Disturb-Tolerant Compute-In-Memory/Digital Rram Macro With Active-Feedback-Based Read And In-Situ Write Verification00.342021
F3 - Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.00.342021
Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems00.342021
Statistical optimization of compute in-memory performance under device variation00.342021
Merged Logic and Memory Fabrics for AI Workloads00.342021
F4 - Electronics for a Quantum World.00.342021
Session 35 Overview - Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee.00.342021
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update10.352021
A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences10.382021
A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics20.382020
Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing20.402020
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.00.342020
31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics.00.342020
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers10.352020
FerroElectronics for Edge Intelligence10.352020
<italic>Learning to Walk</italic>: Bio-Mimetic Hexapod Locomotion via Reinforcement-Based Spiking Central Pattern Generation10.362020
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics00.342020
14.1 A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics30.382019
Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack.20.372019
Direct Feedback Alignment with Sparse Connections for Local Learning.10.422019
Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones00.342019
Computing With Networks of Oscillatory Dynamical Systems.10.372019
Transfer And Online Reinforcement Learning In Stt-Mram Based Embedded Systems For Autonomous Drones00.342019
A 55-nm, 1.0–0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots20.382019
Efficient Signal Reconstruction Via Distributed Least Square Optimization On A Systolic Fpga Architecture00.342019
X-DeepSCA: Cross-Device Deep Learning Side Channel Attack70.592019
Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment10.372019
A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for "In-Sensor" Analytics in Smart Cameras.10.362018
Computing with Coupled Oscillators: Theory, Devices, and Applications00.342018
A Light-Powered Smart Camera With Compressed Domain Gesture Detection.00.342018
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays.00.342018
Smart Sensing for HVAC Control: Collaborative Intelligence in Optical and IR Cameras.00.342018
ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity.50.482018
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.00.342017
  • 1
  • 2