Cross-Layer Resilience: Challenges, Insights, and the Road Ahead | 0 | 0.34 | 2019 |
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). | 3 | 0.40 | 2018 |
Etiss-Ml: A Multi-Level Instruction Set Simulator With Rtl-Level Fault Injection Support For The Evaluation Of Cross-Layer Resiliency Techniques | 1 | 0.37 | 2018 |
System-Level Effects of Soft Errors in Uncore Components. | 4 | 0.41 | 2017 |
Very Low Voltage (Vlv) Design | 0 | 0.34 | 2017 |
Cross-Layer Resilience In Low-Voltage Digital Systems: Key Insights | 1 | 0.35 | 2017 |
Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores. | 0 | 0.34 | 2016 |
The resilience wall: Cross-layer solution strategies | 7 | 0.42 | 2014 |