Author Info
Name
Affiliation
Papers
SHIOMI, J.
Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan|c|
15
Collaborators
Citations 
PageRank 
15
9
5.37
Referers 
Referees 
References 
36
166
53
Search Limit
100166
Title
Citations
PageRank
Year
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics00.342021
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation00.342020
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region00.342020
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator10.402019
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.20.452019
Minimum Energy Point Tracking With All-Digital On-Chip Sensors10.372018
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure00.342018
A Necessary And Sufficient Condition Of Supply And Threshold Voltages In Cmos Circuits For Minimum Energy Point Operation10.362017
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.10.352016
Analytical Stability Modeling For Cmos Latches In Low Voltage Operation00.342016
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing00.342016
Microarchitectural-level statistical timing models for near-threshold circuit design30.402015
Statistical Timing Modeling Based On A Lognormal Distribution Model For Near-Threshold Circuit Optimization00.342015
An energy-efficient on-chip memory structure for variability-aware near-threshold operation00.342015
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring00.342014