| Systolic super summation with reduced hardware | 1 | 0.54 | 1992 |
| Systolic arrays for integer Chinese remaindering | 3 | 0.64 | 1989 |
| Systolic architectures for vector quantization | 36 | 8.17 | 1988 |
| Computer-aided design of VLSI second-order sections | 3 | 1.15 | 1987 |
| A fast tally structure and applications to signal processing. | 0 | 0.34 | 1984 |
| Optimal choice of intermediate latching to maximize throughput in VLSI circuits | 7 | 5.12 | 1983 |
| Some intractable problems in digital signal processing | 0 | 0.34 | 1981 |
