A Simple Method to Reduce Off-chip Memory Accesses on Convolutional Neural Networks. | 0 | 0.34 | 2019 |
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. | 0 | 0.34 | 2017 |
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. | 0 | 0.34 | 2017 |