Satwik A. Patnaik - Citegraph

Author Info

Name	Affiliation	Papers
SATWIK A. PATNAIK	Univ Minnesota, Minneapolis, MN 55455 USA	26
Collaborators	Citations	PageRank
35	64	11.35
Referers	Referees	References
175	516	233

Search Limit

100516

Publications (26 rows)

Collaborators (35 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing	0	0.34	2022
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction	1	0.37	2021
Fa-SAT - Fault-aided SAT-based Attack on Compound Logic Locking Techniques.	0	0.34	2021
On the Vulnerability of Hardware Masking in Practical Implementations	0	0.34	2021
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation	1	0.35	2021
Unsail: Thwarting Oracle-Less Machine Learning Attacks On Logic Locking	2	0.39	2021
Power Side-Channel Attacks in Negative Capacitance Transistor	1	0.38	2020
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging	2	0.36	2020
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets	0	0.34	2020
Spin-based Reconfigurable Logic for Power- and Area-Efficient Applications	1	0.36	2019
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.	0	0.34	2019
3D Integration: Another Dimension Toward Hardware Security	1	0.37	2019
Smart: A Secure Magnetoelectric Antiferromagnet-Based Tamper-Proof Non-Volatile Memory	0	0.34	2019
Protect Your Chip Design Intellectual Property - An Overview.	4	0.41	2019
Attacking Split Manufacturing from a Deep Learning Perspective	3	0.36	2019
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime.	3	0.42	2019
Advancing hardware security using polymorphic and stochastic spin-hall effect devices	7	0.46	2018
Concerted wire lifting: Enabling secure and cost-effective split manufacturing.	5	0.41	2018
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs	2	0.35	2018
Novel Fractional Spur Relocation in All Digital Phase Locked Loops.	0	0.34	2017
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging.	5	0.43	2017
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques.	6	0.45	2017
Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology.	0	0.34	2011
A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS	8	0.85	2009
A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology	3	0.48	2009
Understanding the Transient Behavior of Injection Locked LC Oscillators.	9	1.45	2007