John Wickerson - Citegraph

Author Info

Name	Affiliation	Papers
JOHN WICKERSON	Imperial Coll London, Dept Elect & Elect Engn, Circuits & Syst Res Grp, London, England	19
Collaborators	Citations	PageRank
27	35	7.17
Referers	Referees	References
117	222	78

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100222

Publications (19 rows)

Collaborators (27 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Finding and Finessing Static Islands in Dynamically Scheduled Circuits	0	0.34	2022
C4: the C compiler concurrency checker	1	0.34	2021
An Empirical Study of the Reliability of High-Level Synthesis Tools	2	0.38	2021
Probabilistic Optimization for High-Level Synthesis	0	0.34	2021
Specifying and testing GPU workgroup progress models	0	0.34	2021
The semantics of shared memory in Intel CPU/FPGA systems	1	0.35	2021
Formal verification of high-level synthesis	1	0.36	2021
Fuzzing High-Level Synthesis Tools	0	0.34	2021
Slow and Steady: Measuring and Tuning Multicore Interference	2	0.37	2020
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design.	0	0.34	2020
Precise Pointer Analysis in High-Level Synthesis	0	0.34	2020
Finding and Understanding Bugs in FPGA Synthesis Tools.	0	0.34	2020
Combining Dynamic & Static Scheduling in High-level Synthesis.	1	0.35	2020
Persistency semantics of the Intel-x86 architecture	2	0.37	2020
Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models	2	0.37	2019
The Semantics of Transactions and Weak Memory in x86, Power, ARM, and C++.	3	0.38	2017
Hardware Synthesis of Weakly Consistent C Concurrency.	1	0.38	2017
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis.	4	0.46	2016
A Case for Work-stealing on FPGAs with OpenCL Atomics.	15	0.69	2016

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