Author Info
Name
Affiliation
Papers
MARIO MERCANDELLI
Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy
12
Collaborators
Citations 
PageRank 
29
15
4.32
Referers 
Referees 
References 
50
216
57
Search Limit
100216
Title
Citations
PageRank
Year
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters00.342022
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise00.342022
A 12.9-To-15.1ghz Digital Pll Based On A Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter00.342021
A 98.4fs-Jitter 12.9-To-15.1ghz Pll-Based Lo Phase-Shifting System With Digital Background Phase-Offset Correction For Integrated Phased Arrays00.342021
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs60.462021
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity00.342021
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter00.342021
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<italic>N</italic> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking10.352020
A 66fs(Rms) Jitter 12.8-To-15.2ghz Fractional-N Bang-Bang Pll With Digital Frequency-Error Recovery For Fast Locking00.342020
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.00.342020
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.70.462019
A Background Calibration Technique to Control the Bandwidth of Digital PLLs.10.352018