Masayuki Shimoda - Citegraph

Author Info

Name	Affiliation	Papers
MASAYUKI SHIMODA	Tokyo Institute of Technology, Tokyo, Japan	17
Collaborators	Citations	PageRank
12	8	6.45
Referers	Referees	References
41	77	29

Publications (17 rows)

Collaborators (12 rows)

Referers (41 rows)

Referees (77 rows)

Title	Citations	PageRank	Year
Fpga-Based Inter-Layer Pipelined Accelerators For Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks With Overlapped Tiling	1	0.43	2021
Fast Monocular Depth Estimation on an FPGA	0	0.34	2020
Sentei: Filter-Wise Pruning With Distillation Towards Efficient Sparse Convolutional Neural Network Accelerators	0	0.34	2020
Guinness: A Gui Based Binarized Deep Neural Network Framework For Software Programmers	0	0.34	2019
An FPGA-based Fine Tuning Accelerator for a Sparse CNN.	1	0.35	2019
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation.	2	0.53	2019
Power Efficient Object Detector With An Event-Driven Camera For Moving Object Surveillance On An Fpga	0	0.34	2019
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network	1	0.36	2019
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA	0	0.34	2019
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera	0	0.34	2019
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System	0	0.34	2019
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks	0	0.34	2019
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector	0	0.34	2018
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)	0	0.34	2018
Power Efficient Object Detector With An Event-Driven Camera On An Fpga	0	0.34	2018
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs	0	0.34	2018
All binarized convolutional neural network and its implementation on an FPGA	3	0.72	2017

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