Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| Improving LUT-based optimization for ASICs | 0 | 0.34 | 2022 |
| LUT-Based Optimization For ASIC Design Flow | 0 | 0.34 | 2021 |
| SAT-Sweeping Enhanced for Logic Synthesis | 0 | 0.34 | 2020 |
| Scalable Boolean Methods In A Modem Synthesis Flow | 0 | 0.34 | 2019 |
| Improvements To Boolean Resynthesis | 1 | 0.38 | 2018 |
| Integrated ESOP Refactoring for Industrial Designs | 0 | 0.34 | 2018 |
| Enabling exact delay synthesis. | 2 | 0.37 | 2017 |
| Logic optimization and synthesis: Trends and directions in industry. | 1 | 0.35 | 2017 |