Author Info
Name
Affiliation
Papers
VALERIO MILO
Dipartimento di Elettronica, Informazione e Bioingegneria and Italian Universities Nanoelectronics Team, Politecnico di Milano, Milano, Italy
3
Collaborators
Citations 
PageRank 
17
2
1.06
Referers 
Referees 
References 
13
0
0
Title
Citations
PageRank
Year
Optimized programming algorithms for multilevel RRAM in hardware neural networks10.372021
A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP).10.352018
Stochastic Learning in Neuromorphic Hardware via Spike Timing Dependent Plasticity With RRAM Synapses.00.342018