Author Info
Name
Affiliation
Papers
SHANSHAN LIU
Department of Electronical and Computer Engineering, Northeastern University, Boston, MA, USA
13
Collaborators
Citations 
PageRank 
30
5
4.50
Referers 
Referees 
References 
26
0
0
Title
Citations
PageRank
Year
Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog10.352022
Selective Neuron Re-Computation (SNRC) for Error-Tolerant Neural Networks00.342022
Reduced Precision Redundancy for Reliable Processing of Data00.342021
Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP)10.362021
Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning20.372021
Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design00.342021
High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets00.342021
Analyzing and Assessing Pollution Attacks on Bloom Filters: Some Filters are More Vulnerable than Others00.342021
Scheme for periodical concurrent fault detection in parallel CRC circuits10.382020
Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine00.342020
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes00.342020
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance00.342020
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes00.342019