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HIROSHI NAKAHARA
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Name
Affiliation
Papers
HIROSHI NAKAHARA
Keio Univ, Kohoku Ku, 3-14-1 Hiyoshi, Yokohama, Kanagawa, Japan
8
Collaborators
Citations
PageRank
14
3
2.77
Referers
Referees
References
7
155
68
Search Limit
100
155
Publications (8 rows)
Collaborators (14 rows)
Referers (7 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface
0
0.34
2017
A Layout-Oriented Routing Method For Low-Latency Hpc Networks
0
0.34
2017
A Novel Channel Assignment Method To Ensure Deadlock-Freedom For Deterministic Routing
2
0.39
2017
XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs
1
0.35
2017
Novel Chip Stacking Methods To Extend Both Horizontally And Vertically For Many-Core Architectures With Throuchip Interface
0
0.34
2016
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies
0
0.34
2016
Trax solver on Zynq using incremental update algorithm
0
0.34
2016
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips
0
0.34
2015
1