Author Info
Name
Affiliation
Papers
HYUNSU PARK
Department of Micro/Nano Systems, Korea University, Seoul, South Korea
12
Collaborators
Citations 
PageRank 
28
8
4.24
Referers 
Referees 
References 
34
154
29
Search Limit
100154
Title
Citations
PageRank
Year
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme00.342022
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.00.342022
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations10.352022
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End10.362022
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces20.392022
A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection00.342022
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS00.342021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line00.342021
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector using Bangbang Duty-Cyle-Detector00.342021
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links30.412021
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications00.342020
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.10.362018