Ganesh Gore - Citegraph

Author Info

Name	Affiliation	Papers
GANESH GORE	Electrical and Computer Engineering Department, University of Utah, Salt Lake City, Utah, USA	5
Collaborators	Citations	PageRank
5	1	1.73
Referers	Referees	References
3	30	7

Publications (5 rows)

Collaborators (5 rows)

Referers (3 rows)

Referees (30 rows)

Title	Citations	PageRank	Year
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs	0	0.34	2021
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project	0	0.34	2021
A RRAM-based FPGA for Energy-efficient Edge Computing	0	0.34	2020
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors	1	0.37	2019
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.	0	0.34	2019

1