Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. | 0 | 0.34 | 2022 |
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. | 1 | 0.36 | 2022 |
Polynomial multiplication on embedded vector architectures. | 1 | 0.36 | 2022 |
2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022 | 0 | 0.34 | 2022 |
Analysis and Comparison of Table-based Arithmetic to Boolean Masking. | 0 | 0.34 | 2021 |
Exploring Micro-architectural Side-Channel Leakages through Statistical Testing. | 0 | 0.34 | 2021 |
Hardware-Efficient Post-Processing Architectures for True Random Number Generators. | 0 | 0.34 | 2019 |
SCM: Secure Code Memory Architecture. | 0 | 0.34 | 2017 |
Secure Sketch Metamorphosis: Tight Unified Bounds. | 0 | 0.34 | 2015 |
A systematic M safe-error detection in hardware implementations of cryptographic algorithms | 1 | 0.35 | 2012 |
10281 Abstracts Collection - Dynamically Reconfigurable Architectures. | 0 | 0.34 | 2010 |
Embedded software integration for coarse-grain reconfigurable systems | 16 | 1.06 | 2004 |