A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. | 0 | 0.34 | 2021 |
An Adaptive Equalization Algorithm for High Speed SerDes. | 0 | 0.34 | 2021 |
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits. | 0 | 0.34 | 2021 |
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. | 0 | 0.34 | 2017 |