| Towards Ultra-High Performance and Energy Efficiency of Deep Learning Systems: An Algorithm-Hardware Co-Optimization Framework. | 7 | 0.55 | 2018 |
| Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs. | 4 | 0.54 | 2018 |
| Memristor crossbar-based ultra-efficient next-generation baseband processors | 1 | 0.36 | 2017 |
| CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-Circulant Weight Matrices | 0 | 0.34 | 2017 |
