Author Info
Name
Papers
Collaborators
Y. NAKASE
2
11
Citations 
PageRank 
Referers 
18
2.41
50
Referees 
References 
7
2
Title
Citations
PageRank
Year
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree141.312001
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]41.101997