Shaolin Xie - Citegraph

Author Info

Name	Affiliation	Papers
SHAOLIN XIE	University of Washington, Seattle, WA	2
Collaborators	Citations	PageRank
31	0	0.68
Referers	Referees	References
0	0	0

Publications (2 rows)

Collaborators (31 rows)

Referers (0 rows)

Referees (0 rows)

Title	Citations	PageRank	Year
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm	0	0.34	2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS	0	0.34	2019

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