Title
State Verification
Abstract
State verification is a more restricted problem than state identification, discussed in Chapter 2. As in state verification, we know the state diagram of the system under test. The difference is that we have an assumption about which state the system is currently in, and the objective is to check that this assumption is correct. The basic idea is that when testing a machine, we can give it an input sequence, and then use state verification to verify that the sequence took the machine under test to the expected state.
Year
DOI
Venue
2004
10.1007/11498490_4
Model-Based Testing of Reactive Systems
DocType
Citations 
PageRank 
Conference
1
0.35
References 
Authors
1
1
Name
Order
Citations
PageRank
Henrik Björklund131120.41