Paper Info
Title
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
Abstract
Latest evaluation of the state-of-the-art iMDPL logic style has shown small information leakage compared to its predecessor version MDPL. Concurrently, new advanced power analysis attacks specifically targeting iMDPL have been proposed. Up to now, these attacks are purely theoretic and have not been applied to an implementation. We present a comprehensive analysis of iMDPL, backed by real measurements collected from a 180 nm iMDPL prototype chip. We thoroughly study the extent of remaining information leakage of iMDPL by applying all relevant attacks. Our investigation shows the vulnerability of the target device, a standalone AES core, to several of the advanced attack methods. In comparison to conventional power analysis attacks, the advanced attacks need less power measurements to obtain meaningful results. With the help of logic level simulations routing imbalances between complementary mask trees are identified as a major source of leakage.
Year
DOI
Venue
2012
10.1109/TVLSI.2011.2160375
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
cryptography,logic design,logic simulation,iMDPL logic style,iMDPL prototype chip,information leakage,logic level simulation,masked dual-rail precharge logic,power analysis,vulnerability,AES,correlation,cryptography,delay,dual-rail precharge logic,encryption,energy consumption,iMDPL,logic design,masking,power analysis
Logic synthesis,Power analysis,Logic gate,Information leakage,Cryptography,Computer science,Real-time computing,Electronic engineering,Encryption,Logic simulation,Logic level,Embedded system
Journal
Volume
Issue
ISSN
20
9
1063-8210
Citations 
PageRank 
References 
7
0.60
21
Authors
4
Name
Order
Citations
PageRank
Amir Moradi196080.66
Mario Kirschbaum216310.59
Thomas Eisenbarth384061.33
Christof Paar43794442.62