Name
Abstract | ||
|---|---|---|
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, such as the transition fault model and the path-delay model, have been used to aid delay defect detection. However, these models are not efficient for small-delay defect coverage or for test pattern generation time. Error sequence analysis utilizes the order in which the errors occur during a frequency sweep of a transition test to identify small- delay defects that may escape the same test applied in the conventional way. Moreover, it can detect such defects even in the presence of inter-die process variations, such as lot-to-lot and wafer-to-wafer process variation. In addition, error sequence analysis is very effective in separating devices with delay defects from devices that have failed due to process variation. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/VTS.2008.45 | VTS |
Keywords | Field | DocType |
integrated circuit testing,ic process,transition fault model,test pattern generation time,path-delay model,ic process variation,inter-die process variation,automatic test pattern generation,fault diagnosis,wafer-to-wafer process variation,error sequence analysis,interdie process variations,transition test,delay defect detection,small-delay defect,delay defect,process variation,logic gates,fault model,threshold voltage,sequence analysis,time frequency analysis | Automatic test pattern generation,Logic gate,Computer science,Operating speed,Electronic engineering,Real-time computing,Time–frequency analysis,Process variation,Sweep frequency response analysis,Fault model,Sequence analysis | Conference |
ISSN | ISBN | Citations |
1093-0167 | 978-0-7695-3123-6 | 0 |
PageRank | References | Authors |
0.34 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaekwang Lee | 1 | 17 | 7.06 |
| Intaik Park | 2 | 22 | 2.36 |
| Edward J. Mccluskey | 3 | 3868 | 501.21 |