Name
Abstract | ||
|---|---|---|
Abstract: Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. To overcome this problem researchers choose a very small portion ... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/PACT.2001.953287 | IEEE PACT |
Keywords | Field | DocType |
reactive-associative caches,problem researcher,full execution,small portion,detailed pipeline simulation,modern architecture research,industry standard benchmark,degradation,hitting time,data engineering,bandwidth,feedback,feedback mechanism,instruction sets | Cache-oblivious algorithm,Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Smart Cache | Conference |
ISBN | Citations | PageRank |
0-7695-1363-8 | 38 | 2.78 |
References | Authors | |
16 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Brannon Batson | 1 | 270 | 21.72 |
| T. N. Vijaykumar | 2 | 2560 | 169.28 |