Name
Abstract | ||
|---|---|---|
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-induced variation is reduced by 3dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1391469.1391557 | DAC |
Keywords | Field | DocType |
analogue circuits,parallel processing,voltage-controlled oscillators,analog parallelism,chip-limited yield,parallel ring-based VCOs,phase noise,within-chip process-induced variation,Analog parallelism,clock period jitter,microprocessor,phase noise,phase-locked loop,process-induced variation,ring-based voltage-controlled oscillator | Analogue circuits,Phase-locked loop,Computer science,Microprocessor,Parallel processing,Phase noise,Real-time computing,Electronic engineering,Jitter | Conference |
ISSN | Citations | PageRank |
0738-100X | 0 | 0.34 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daeik D. Kim | 1 | 27 | 5.49 |
| Choongyeun Cho | 2 | 40 | 6.76 |
| Jonghae Kim | 3 | 101 | 14.95 |